2.6 Hierarchical Circuit Design

The Schematic Editor provides functions for creating hierarchical schematic designs. Through these functions it is possible to define schematic sheets to be sub-blocks and to reference sub-blocks from higher level schematic plans. This high-sophisticated SCM design feature is recommended especially for experienced users designing large projects with replicated parts of the circuitry. Hierarchical circuit design usually is applied for the development of integrated circuits such as gate arrays, standard cells or ASICs.

2.6.1 Sub-block Circuit Drawing

The schematics for the sub-block can be defined on one or more sheets. The Sub-Block option of the Set Sheet Blockname function from the Settings dialog is used for assigning a sub-block name to the sub-block circuit drawing. Identical sub-block names must be set for different sheets defining the same sub-block. Figure 2-10 shows an example for a sub-block circuit drawing named BLOCK. Connections to higher hierarchy levels (i.e., the sub-block's pins) are defined by module ports. The system uses a standard label symbol named port for module ports. The Add Module Port function from the Symbols menu is used for defining and placing module ports. The Move Symbol/Label and Delete Symbol/Label functions from the Symbols menu can be used for moving and/or deleting module ports. In figure 2-10 the module ports S, R, Q, /Q and HYPER are defined. Within hierarchical circuit design there is a difference between global and local net names. A local net is defined by preceding the net name with an ampersand (&) character. Hence the nets named &ABC and /&ABC in figure 2-10 are defined locally in all sheets with the same blockname. Standard net name allocation (such as at VCC) introduces a global net definition which connects on all sheets, no matter what hierarchy level the net name is defined on. When using a global net name in a sub-block, all matching nets from multiple referenced sub-blocks are connected as well.

Figure 2-10: Hierarchical Circuit Design; Sub-Block SCM Sheet "BLOCK"

The Set Sheet Blockname parameter setting also provides the Single Sub-Block option for block diagramming support. Whilst there are multiple references to a standard Sub-Block allowed, a Single Sub-Block sheet can only be referenced once. Single sub-blocks are treated like normal SCM sheets by Packager and Backannotation. I.e., the Packager transfers symbol/part names from single sub-blocks without [Pn] prefices to the layout, and Backannotation transfers part name changes and pin/gate swaps on single sub-blocks back to the schematics.

2.6.2 Sub-block Reference Symbol and Logical Sub-block Reference

A special SCM symbol is required for referencing any sub-block on higher hierarchy levels. The pin names of that symbol must match the names of the module ports defined on the corresponding sub-block circuit drawing.

The Packager needs a logical reference for any sub-block reference symbol used throughout the schematics. This logical reference must be created in the Logical Library by defining a logical library file entry for the sub-block reference symbol. This loglib entry must define a virtual part with the name of the sub-block reference symbol. For referencing the sub-block, the loglib command call (with the blockname of the sub-block as argument) must be used. See also chapter 7.11 of this manual for a more detailed description of the loglib utility program.

Figure 2-11 shows the sub-block reference symbol DFF and the corresponding logical sub-block reference for the sub-block circuit drawing in figure 2-10. Note that figure 2-11 also illustrates how to define busses on sub-block reference symbols.

Figure 2-11: Hierarchical Circuit Design; Block Symbol "DFF" with Loglib Definition

2.6.3 Top Level Circuit Drawing

Figure 2-12 shows how the sub-block symbol DFF from figure 2-11 is used in a higher level schematic drawing. The circuit drawing in figure 2-12 contains three DFF symbols named DFF_1, DFF_2 and DFF_3, each referencing one BLOCK sub-block circuit drawing.

Figure 2-12: Hierarchical Circuit Design; Top Level SCM Sheet

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