Bartels :: Bartels AutoEngineer :: BAE Documentation :: BAE User Manual |
The Bartels AutoEngineer® - User Manual describes in detail how to use the Bartels AutoEngineer CAE/CAD/CAM design system. The following main topics are covered by this manual:
Last Change
Bartels AutoEngineer® - User Manual | 11/11/2009 |
![]() | Preface |
![]() | Organization of this Documentation |
![]() | Related Documentation |
![]() | Problems, Questions, Suggestions |
![]() | Documentation Notations | 11/10/2010 |
![]() | Documentation Conventions | 11/10/2010 |
![]() | Copyright | 16/11/2007 |
![]() | 1 | Introduction | 26/01/2007 |
![]() | 1.1 | Product Information | 16/10/2007 |
![]() | 1.1.1 | BAE Software Configurations |
![]() | 1.1.2 | BAE System Components |
![]() | 1.1.3 | BAE Database Structure |
![]() | 1.1.4 | BAE Data Types and Application Concepts |
![]() | 1.1.5 | Exchanging Data with other Systems |
![]() | 1.2 | Operating the Bartels AutoEngineer | 03/09/2010 |
![]() | 1.2.1 | BAE Startup and BAE User Interface |
![]() | 1.2.2 | Function Selection |
![]() | 1.2.3 | Basic System Functions |
![]() | 1.2.4 | Graphic Input |
![]() | 1.2.5 | Special Remarks |
![]() | 1.3 | BAE Design Database | 26/01/2007 |
![]() | 1.3.1 | Database Concept |
![]() | 1.3.2 | SCM Database Hierarchy |
![]() | 1.3.3 | Layout Database Hierarchy |
![]() | 1.3.4 | Logical Library |
![]() | 2 | Circuit Design / CAE | 02/12/2006 |
![]() | 2.1 | General | 22/12/2010 |
![]() | 2.1.1 | Components and Features |
![]() | 2.1.2 | Starting the Schematic Editor |
![]() | 2.1.3 | Schematic Editor Main Menu |
![]() | 2.1.4 | Customized Schematic Editor User Interface |
![]() | 2.1.5 | In-built Schematic Editor System Features |
![]() | 2.2 | SCM Library Symbol Design | 11/10/2010 |
![]() | 2.2.1 | Creating SCM Markers |
![]() | 2.2.2 | Creating SCM Symbols |
![]() | 2.2.3 | Creating SCM Labels |
![]() | 2.3 | Designing SCM Circuits | 11/10/2010 |
![]() | 2.3.1 | Creating and Editing SCM Plans |
![]() | 2.3.2 | Symbols |
![]() | 2.3.3 | Connections, Labels, Busses |
![]() | 2.3.4 | Text and Graphic |
![]() | 2.4 | Special SCM Functions | 11/10/2010 |
![]() | 2.4.1 | Virtual Symbols |
![]() | 2.4.2 | Groups |
![]() | 2.4.3 | Plug Pin Assignment |
![]() | 2.4.4 | Net Attributes |
![]() | 2.4.5 | Tag Symbols |
![]() | 2.4.6 | Templates |
![]() | 2.4.7 | Exiting the Schematic Editor |
![]() | 2.5 | SCM Plot Output | 24/10/2010 |
![]() | 2.5.1 | General Plot Parameters |
![]() | 2.5.2 | HP-GL Pen Plot |
![]() | 2.5.3 | HP-Laser Output |
![]() | 2.5.4 | Postscript Output |
![]() | 2.5.5 | Generic Output under Windows |
![]() | 2.5.6 | Bitmap Plot Output to Windows Clipboard |
![]() | 2.6 | Hierarchical Circuit Design | 02/10/2007 |
![]() | 2.6.1 | Sub-block Circuit Drawing |
![]() | 2.6.2 | Sub-block Reference Symbol and Logical Sub-block Reference |
![]() | 2.6.3 | Top Level Circuit Drawing |
![]() | 2.7 | Backannotation | 05/03/2007 |
![]() | 3 | Packager / Backannotation | 26/01/2007 |
![]() | 3.1 | General | 26/01/2007 |
![]() | 3.1.1 | Components and Features |
![]() | 3.2 | Packager | 03/09/2010 |
![]() | 3.2.1 | Starting the Packager |
![]() | 3.2.2 | Packager Main Menu |
![]() | 3.2.3 | Running the Packager |
![]() | 3.2.4 | Example |
![]() | 3.2.5 | Messages |
![]() | 3.3 | Backannotation | 05/03/2007 |
![]() | 3.3.1 | Starting the Backannotation |
![]() | 3.3.2 | Running the Backannotation |
![]() | 3.3.3 | Example |
![]() | 3.4 | Net List Utilities | 26/01/2007 |
![]() | 3.4.1 | Importing Logical Net Lists |
![]() | 3.4.2 | Importing Physical Net Lists |
![]() | 3.4.3 | Exporting Net List Data |
![]() | 3.4.4 | Net Attributes |
![]() | 4 | PCB Design / CAD | 05/03/2007 |
![]() | 4.1 | General | 06/12/2010 |
![]() | 4.1.1 | Components and Features |
![]() | 4.1.2 | Starting the Layout System |
![]() | 4.1.3 | Layout Editor Main Menu |
![]() | 4.1.4 | Customized Layout Editor User Interface |
![]() | 4.1.5 | In-built Layout System Features |
![]() | 4.2 | Layout Library Symbol Design | 11/10/2010 |
![]() | 4.2.1 | Creating Layout Pads |
![]() | 4.2.2 | Creating Layout Padstacks |
![]() | 4.2.3 | Creating Layout Parts |
![]() | 4.3 | Designing PCB Layouts | 11/10/2010 |
![]() | 4.3.1 | Creating and Editing PCB Layouts |
![]() | 4.3.2 | Parts, Placement |
![]() | 4.3.3 | Text and Graphic |
![]() | 4.3.4 | Traces, Routing |
![]() | 4.4 | Autoplacement | 11/10/2010 |
![]() | 4.4.1 | Part Set |
![]() | 4.4.2 | Matrix Placement |
![]() | 4.4.3 | Initial Placement |
![]() | 4.4.4 | Placement Optimization |
![]() | 4.5 | Autorouter | 11/10/2010 |
![]() | 4.5.1 | Starting the Autorouter |
![]() | 4.5.2 | Autorouter Main Menu |
![]() | 4.5.3 | Customized Autorouter User Interface |
![]() | 4.5.4 | In-built Autorouter System Features |
![]() | 4.5.5 | Autorouter Options |
![]() | 4.5.6 | Autorouter Control |
![]() | 4.5.7 | Autorouter Strategy |
![]() | 4.5.8 | Autorouter Functions |
![]() | 4.5.9 | Using the Autorouter |
![]() | 4.6 | Special Layout Features | 11/10/2010 |
![]() | 4.6.1 | Batch Design Rule Check, Report |
![]() | 4.6.2 | Color Setup, Color Tables, Pick Preference Layer |
![]() | 4.6.3 | Layout Net List Changes |
![]() | 4.6.4 | SCM Changes, Redesign |
![]() | 4.6.5 | Defining and Editing Power Layers |
![]() | 4.6.6 | Autorouter Via Keepout Areas |
![]() | 4.6.7 | Area Mirror Mode |
![]() | 4.6.8 | Automatic Copper Fill |
![]() | 4.6.9 | Library Update |
![]() | 4.6.10 | Back Net List |
![]() | 4.6.11 | Blind and Buried Vias |
![]() | 4.6.12 | Exiting the Layout System |
![]() | 4.7 | CAM Processor | 22/12/2010 |
![]() | 4.7.1 | Starting the CAM Processor |
![]() | 4.7.2 | CAM Processor Main Menu |
![]() | 4.7.3 | Customized CAM Processor User Interface |
![]() | 4.7.4 | In-built CAM Processor System Features |
![]() | 4.7.5 | Plot Parameters |
![]() | 4.7.6 | Power Layers |
![]() | 4.7.7 | HP-GL Output |
![]() | 4.7.8 | HP Laser Output |
![]() | 4.7.9 | Postscript Output |
![]() | 4.7.10 | Windows Generic Output |
![]() | 4.7.11 | Bitmap Plot Output to Windows Clipboard |
![]() | 4.7.12 | Gerber Photoplot |
![]() | 4.7.13 | Drill Data |
![]() | 4.7.14 | Insertion Data |
![]() | 4.8 | CAM View | 11/10/2010 |
![]() | 4.8.1 | Starting the CAM View Module |
![]() | 4.8.2 | CAM View Main Menu |
![]() | 4.8.3 | Customized CAM View User Interface |
![]() | 4.8.4 | In-built CAM View System Features |
![]() | 4.8.5 | Processing Gerber Data |
![]() | 4.8.6 | Processing Drilling and Milling Data |
![]() | 4.8.7 | Retrieving Layouts from Gerber Data |
![]() | 5 | IC/ASIC Design | 26/01/2007 |
![]() | 5.1 | General | 11/10/2010 |
![]() | 5.1.1 | Components and Features |
![]() | 5.1.2 | IC Design System Startup |
![]() | 5.1.3 | Chip Editor Main Menu |
![]() | 5.1.4 | Chip Editor User Interface |
![]() | 5.1.5 | Chip Editor System Features |
![]() | 5.2 | IC Cell Library | 11/10/2010 |
![]() | 5.2.1 | IC Pin Definitions |
![]() | 5.2.2 | IC Cell Definitions |
![]() | 5.3 | IC Mask Layout | 11/10/2010 |
![]() | 5.3.1 | Creating and Editing Chip Layouts |
![]() | 5.3.2 | Cell Makros, Placement |
![]() | 5.3.3 | Text and Graphic |
![]() | 5.3.4 | Traces, Routing |
![]() | 5.4 | Cell Placer | 26/01/2007 |
![]() | 5.4.1 | Cell Placer Startup |
![]() | 5.4.2 | Cell Placer Main Menu |
![]() | 5.4.3 | Cell Placer System Features |
![]() | 5.4.4 | Cell Placer Options |
![]() | 5.4.5 | Cell Placer Control |
![]() | 5.4.6 | Cell Placer Functions |
![]() | 5.5 | Cell Router | 11/10/2010 |
![]() | 5.5.1 | Cell Router Startup |
![]() | 5.5.2 | Cell Router Main Menu |
![]() | 5.5.3 | Cell Router System Features |
![]() | 5.5.4 | Cell Router Options |
![]() | 5.5.5 | Cell Router Control |
![]() | 5.5.6 | Cell Router Strategy |
![]() | 5.5.7 | Cell Router Functions |
![]() | 5.6 | IC Design Data Import and Export | 06/02/2006 |
![]() | 5.6.1 | GDS Data Import and Output |
![]() | 5.6.2 | CIF Data Import and Output |
![]() | 6 | Neural Rule System | 26/01/2007 |
![]() | 6.1 | General | 26/01/2007 |
![]() | 6.2 | Rule Definition | 26/01/2007 |
![]() | 6.2.1 | Bartels Rule Specification Language |
![]() | 6.2.2 | Bartels Rule System Compiler |
![]() | 6.3 | Rule System Applications | 09/11/2013 |
![]() | 6.3.1 | Circuit Design Rule System Applications |
![]() | 6.3.2 | PCB Design Rule System Applications |
![]() | 6.4 | Rule System Predicates | 05/03/2007 |
![]() | 6.4.1 | Circuit Design Rule System Predicates |
![]() | 6.4.2 | PCB Design Rule System Predicates |
![]() | 7 | Utilities | 26/01/2007 |
![]() | 7.1 | BAEHELP | 25/01/2006 |
![]() | 7.2 | BAESETUP, BSETUP | 18/03/2011 |
![]() | 7.3 | BICSET (IC Design) | 28/01/2010 |
![]() | 7.4 | BLDRING (IC Design) | 28/01/2010 |
![]() | 7.5 | CONCONV | 26/01/2007 |
![]() | 7.6 | COPYDDB | 11/10/2010 |
![]() | 7.7 | FONTCONV | 26/01/2007 |
![]() | 7.8 | FONTEXTR | 26/01/2007 |
![]() | 7.9 | INSTALL | 26/01/2007 |
![]() | 7.10 | LISTDDB | 11/10/2010 |
![]() | 7.11 | LOGLIB | 18/11/2011 |
![]() | 7.12 | NETCONV | 11/10/2010 |
![]() | 7.13 | REDASC | 11/10/2010 |
![]() | 7.14 | RULECOMP | 26/01/2007 |
![]() | 7.15 | ULC - User Language Compiler | 11/10/2010 |
![]() | 7.16 | User Language Interpreter | 05/03/2007 |
![]() | 7.17 | USERLIST | 13/02/2009 |
![]() | 7.18 | VALCONV | 11/10/2010 |
Bartels :: Bartels AutoEngineer :: BAE Documentation :: BAE User Manual |
Bartels AutoEngineer® - User Manual
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