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NOTE This chapter describes how to use the Chip Editor (IC Mask Editor), Cell Placer, and Cell Router program modules for the physical design of IC and/or ASIC mask layouts. The GDS View and CIF View program modules for importing and/or checking cell libraries and/or IC mask data in GDS and CIF format are also introduced. Unfortunately, we can't provide real design examples in this chapter because the IC manufacturing process parameters and the cell libraries of logical primitives are usually provided by the manufacturer. Although your manufacturer is unlikely to charge anything for the provision of such data in a format suitable for import into the Bartels AutoEngineer (such as GDS), the publication of this data is usually strictly prohibited by a non disclosure agreement (NDA). Contents
5.1 GeneralThe Bartels AutoEngineer IC Design system essentially consists of an interactive Chip Editor (IC Mask Editor) with integrated cell/macro symbol editor and comprehensive design rule checking facilities, Cell Placer for automatic standard cell placement, and the Cell Router for automatic IC layout routing. GDS View and CIF View program modules for importing and/or checking cell libraries and/or IC mask data in GDS and/or CIF format are also included in the software. 5.1.1 Components and FeaturesChip EditorThe floating point database used throughout the BAE Chip Editor allows for the mixed specification of metric (mm, µm) and imperial (Inch, mil) coordinate units. All placement coordinates including rotation angles can be specified with floating point values. There are no restrictions at the definition and placement of pin areas, active areas, cells, traces, texts, etc. The user interface accurately displays even the more complex structures such as circles or arcs. The Design Rule Check (DRC) operates in grid-free mode with a precision of eight digits behind the decimal point. The DRC provides constant monitoring of connection areas and traces/pins against the net list, with visual indication of distance violations and short-circuits. The system supports both Online and Batch DRC. Online DRC performs incremental checks, i.e., only the modified items are checked real-time thus saving computation time. The facilities allow to use the Chip Editor without fear of causing damage. Up to twenty commands can be reversed or undone by applying the function and then reprocessed with the function. ensures data security and provides a powerful feature for estimating design alternatives. Arbitrary parts of the chip layout can be selected to groups and then moved, rotated, mirrored, copied or saved (and subsequently used as templates). Fast interactive cell placement with instant connections update guarantees an optimum exploitation of the chip area. Connections (unroutes, airlines) are dynamically calculated and instantly displayed during placement. Cells can scaled, mirrored and rotated at arbitrary angles. Cells can be placed at arbitrary coordinates and polar coordinates are supported for placing cells on a circle. The cell library supports cell-specific preferences for rotation and mirroring. During manual placement, alternative cell definition (as configured in the cell library) can be selected for the currently processed cell. The system supports genuine net-orientated Connectivity. This means that electrical connections can be realized through connection areas instead of traces connecting. Traces and connection areas can be created in grid-free mode with floating point precision. Highlight is used to indicate the selected and/or processed signal, and each point of the signal can be connected. The system also supports partial vias with automatic via type selection. Active areas can be resized using arbitrary expansion values. Trace segment lengths and active area edge lengths can automatically be determined or measured for test or documentation purposes. With the Bartels User Language integrated to the Chip Editor the user is able to implement enhanced CAD functions and macros, user-specific import and export functions, report and test functions, etc. User Language programs can be called by applying the function from the menu or by pressing a key on the keyboard (hot key). Cell PlacerSorry, this information is currently being updated. Cell RouterThe Cell Router is used for automatically routing the traces of the chip layout. The Cellrouter kernel is based on the well-known Bartels AutoEngineer with its highly sophisticated backtracking and rip-up/retry algorithms. These type of routing algorithms are capable of achieving 100% route completion where other routers fail. Extensive artificial intelligence features are built into the router to produce high quality design results in a reasonable time. The Cell Router includes special features for optimizaing the routing for IC mask production. The complete routing process is supervised by a backtracking algorithm. This backtracking prevents from a deterioration of the routing result or a dead-lock during rip-up or optimization and is capable to exploit new and/or better routing solutions. Both the selective rip-up and the cross-net optimizer passes are assisted by a unique intelligent multi-net cleanup algorithm. This algorithm identifies traces and/or trace segments which are blocking other conncetions and rips up and reroutes multiple connections or even trees at a time to improve the global routing result. The Cell Router is capable of moving trace bunches to make space for not yet routed connections (push'n'shove routing). Cleanup passes for performing cross-net changes are applied during optimization and will considerably reduce via counts and straighten trace paths. All advanced routing features are supported by a sophisticated array of heuristic cost parameters which can be dynamically adapted to produce quality routing results comparable to those made by skilled layout designers. The Cell Router is capable of simultaneously routing up to 12 layers. The Cell Router automatically identifies and connects pre-placed traces and active connection areas. The routing width is pin-specific rather than net-specific. T-shaped connections are automatically generated (full copper sharing). The routing progress can be watched both graphically and on statistical readout on the Cell Router user interface. The Cell Router can be stopped at any time and then continued or re-started with changed parameters on demand. The Cell Router provides features and functions for automatically adapting the chip layout to placement and/or net list changes (re-entrant routing) where the Cell Router evaluates pre-routed traces, identifies and removes wrong and redundant paths and short-circuits, and then (re-)routes open connections to achieve a correct 100% solution. Subsequently, the modified chip layout can be optimized again. All of today's advanced chip technologies are fully supported by the Cellrouter. The Cellrouter is able to consider and/or connect arbitrarily shaped pin definitions, traces, connection areas and keepout areas. The built-in off-grid recognition allows for the off-grid placement of cells, pins and pre-routed traces. The Cellrouter supports the selection of arbitrary routing grids with optional half-grid routing. The Cellrouter also maintains partial vias with automatic via type selection to increase the routability of chip layouts with more than two layers. Area and block routing methods can be supported by defining keepout routing areas and/or prohibited layers, and the Cellrouter is also able to consider via keepout areas. GDS ViewGDS View is a graphic program for displaying GDS-II files and/or GDS-II file elements for visual checks. An option is provided to select top level structures only or all hierarchy levels when loading GDS-II data. Zoom functions and color assignment facilities are provided for displaying the data once it's loaded. GDS-View provides a function for saving the currently loaded GDS data as standard cell library element to the Bartels AutoEngineer IC Design system and a batch utility for importing GDS-II standard cell libraries to the Bartels AutoEngineer IC Design system. CIF ViewCIF View is a graphic program for displaying CIF files and/or CIF file elements for visual checks. A scaling factor can be set for loading CIF data. Zoom functions and color assignment facilities are provided for displaying the data once it's loaded. 5.1.2 IC Design System StartupUnless you work on a system with multi-windowing and advanced directory and file selection dialogs, it is recommended to start the
Bartels AutoEngineer from the directory where the design files should be generated since this considerably simplifies job file access. If you intend to process the examples provided with this manual it is recommended to move to the BAE examples directory
> bae Modern operating system with multi-windowing support provide more convenient features for activating the BAE main menu. Under Windows, a BAE program group with the function for activating the BAE main menu is installed to the menu. And it's also not all that important to work from your project directory if your system provides sophisticated file and/or directory selection dialogs. The BAE Main Menu displays the Bartels logo and the following menu:
The function is only available under Windows and/or Motif. The is only available in BAE HighEnd and BAE IC Design. The menu item is only provided with the BAE IC Design system. Move the menu cursor to the menu item and confirm this choice by pressing the left mouse button:
The Chip Editor program module is loaded and the Chip Editor menu is activated. Check your BAE software installation if this fails to happen (see the Bartels AutoEngineer® Installation Guide for details on how to perform a correct installation). 5.1.3 Chip Editor Main MenuDepending on the operating system platform, the Bartels AutoEngineer can be operated with different user interfaces and/or menu configurations. The standard/sidemenu user interface is available on all platforms and provides a menu area on the right side, consisting of the main menu on top and the currently active menu below that main menu. After entering the Chip Editor the menu is active and the menu cursor points to the function. The Windows and Motif versions of the Chip Editor can optionally be operated with a pull-down menu user interface providing a horizontally arranged main menu bar on top. The dialog from the BAE main menu can be used to select the desired menu configuration. When selecting the pulldonw menu configuration, the option also provides a choice for assigning repeat function and the context popup menu to the right and left or left and right mouse buttons. The Chip Editor main menu is always available and provides the following menus and/or functions:
Undo, RedoThe functions provided with the menu allow you to use the Chip Editor without fear of causing damage. Up to twenty commands can be reversed or undone using and then reprocessed with the . This is true even for complex processing such as group functions or User Language program execution. ensures data security and provides a powerful feature for estimating design alternatives. DisplayThe or menu can either be activated by selecting the corresponding main menu item or by pressing the middle mouse button. Activation through the middle mouse button is even possible whilst performing a graphical manipulation such as placing or moving an object. The or menu provides useful functions for changing display options such as zoom window, zoom scale, input and/or display grids, grid and/or angle lock, color settings, etc. The or menu also contains advanced display functions such as and . FilesThe menu provides functions for creating, loading, saving, copying, replacing and deleting DDB elements. The menu also allows to load and/or store color tables or to call important database management functions such as listing DDB file contents and performing library update. MacrosThe provides functions for manual cell placement, for cell renaming and for manual optimization (component swap, pin/gate swap). The function for selecting the via(s) for subsequent routing is also provided in this menu. On cell level, the menu is used for placing, moving, deleting and renaming pins. TracesThe menu provides functions for interactive routing, i.e. for manually creating new traces and for modifying or deleting existing traces and/or trace segments. AreasThe menu is used for defining the chip outline, for generating connection areas and for creating documentary lines and/or documentary areas. Existing areas can be moved, rotated, mirrored, copied and deleted. TextThe menu is used for creating, moving, changing and deleting texts on any layout hierarchy level. GroupsThe menu provides functions for selecting elements to group, for moving, rotating, mirroring, scaling, copying, deleting, fixing, releasing, saving and loading groups, and for replacing symbols in a group. ParameterThe menu provides functions for selecting the layout library, setting the origin and the element boundaries of the currently loaded element, selecting the mincon function for the airline display and activating the automatic design data backup feature. UtilitiesThe menu provides functions for exiting BAE, returning to the BAE main shell, calling the Cell Placer, the Cell Router or GDS View, starting the , displaying a status and starting User Language programs. 5.1.4 Chip Editor User InterfaceMenu Assignments and Key BindingsThe BAE software comes with User Language programs for activating a modified Chip Editor user interface with many additional functions (startups, toolbars, menu assignments, key bindings, etc.). The bae_st User Language program is automatically started when entering the Chip Editor. bae_st calls the uifsetup User Language program which activates predefined Chip Editor menu assignments and key bindings. Menu assignments and key bindings can be changed by modifiying and re-compiling the uifsetup source code. The hlpkeys User Language program is used to list the current key bindings. With the predefined menu assignments of uifsetup activated, hlpkeys can be called from the function of the menu. Menu assignments and key bindings can be listed with the uifdump User Language program. The uifreset User Language program can be used to reset all currently defined menu assignments and key bindings. uifsetup, uifdump and uifreset can also be called from the menu of the keyprog User Language program which provides additional facilities for macro programming, online key assignments, and menu programming and menu configuration. Sorry, this information is currently being updated. 5.1.5 Chip Editor System FeaturesSorry, this information is currently being updated. Net ListA net list is usually required for the design of the chip layout. In BAE, the net list is commonly created with the Schematic Editor and then transferred to the IC Design system using the Packager. Alternatively, ASCII net lists can be imported to the AutoEngineer system using the netconv utility program or customized User Language programs. See chapter 3 of this manual for more details on net list processing. The function for loading a chip layout will not only load the pertinent data from the lower hierarchy levels (cells and pins), but also the corresponding net list. The net list data is correlated with all geometrical data on the chip layout ("Connectivity Generation"). Please note that the element names for both the chip layout and the net list must be identical for this to work. After successfully generating the connectivity, the system is capable of instantly controlling and/or correlating each layout modification with the net list definitions. This highly sophisticated design feature is called "True Connectivity" and enables real-time recognition of electrical connections, no matter whether connections are created through traces, connection areas or vias. I.e., the system supports advanced routing features such as cross connection recognition, genuine T-connections, lining up traces created with group copying, implementing connections with arbitrarily shaped connection areas, etc. Sorry, this information is currently being updated. 5.2 IC Cell LibrarySorry, this information is currently being updated. 5.2.1 IC Pin DefinitionsSorry, this information is currently being updated. 5.2.2 IC Cell DefinitionsSorry, this information is currently being updated. 5.3 IC Mask LayoutSorry, this information is currently being updated. 5.3.1 Creating and Editing Chip LayoutsSorry, this information is currently being updated. 5.3.2 Cell Makros, PlacementSorry, this information is currently being updated. 5.3.3 Text and GraphicSorry, this information is currently being updated. 5.3.4 Traces, RoutingSorry, this information is currently being updated. 5.4 Cell Placer5.4.1 Cell Placer StartupThe function from the Chip Editor menu is used to start the Cell Placer. The system automatically saves the currently loaded chip layout and/or IC design element before the Cell Placer is activated. 5.4.2 Cell Placer Main MenuThe main menu of the Cell Placer provides the following menus and/or functions:
The menu can either be activated by selecting the corresponding main menu item or by pressing the middle mouse button. The menu provides useful functions for changing display options such as zoom scale and display color settings. The menu provides the functions for loading a chip layout for automatic placement, for loading standard cell placement parameters, saving the currently loaded chip layout/placement and examining project file contents. The provides the functions for starting the actual standard cell placement procedures. The menu provides the facilities for defining the placement matrix for subsequent standard cell placement procedures. The menu provides functions for setting certain strategy parameters and heuristic cost factors for the placement procedures. The menu provides functions for exiting the AutoEngineer and/or Cell Placer session, returning to the Chip Editor and a function for estimating the required placement area and for examining the current placement completion status. 5.4.3 Cell Placer System FeaturesSorry, this information is currently being updated. 5.4.4 Cell Placer OptionsSorry, this information is currently being updated. 5.4.5 Cell Placer ControlSorry, this information is currently being updated. 5.4.6 Cell Placer FunctionsSorry, this information is currently being updated. 5.5 Cell RouterThe IC design system of the BAE software provides the Cell Router module for automatically routing the chip layout. With real jobs you should make sure any pre-routed critical traces are fixed, before starting the autorouting process. After finishing the autorouting, you should always run a before generating the data for the IC production. 5.5.1 Cell Router StartupThe function from the Chip Editor menu is used to start the Cell Router. The Cell Router module can only be activated if a chip layout is loaded in the Chip Editor. A chip outline (to be defined with the function from the Chip Editor menu) and a valid via assignment list (use function from the Chip Editor menu) is required by the Cell Router. Please make also sure that all net list cells are placed with correct cell definitions inside the chip outline (no cell or pin and no fixed trace or via must be placed outside the chip outline) before starting the Cell Router. After activating the function, the system automatically saves the currently loaded chip layout and the Cell Router program module starts. The following error messages might be issued when calling the Cell Router and/or within the Cell Router itself:
5.5.2 Cell Router Main MenuThe main menu of the Cell Router provides the following menus and/or functions:
The menu can either be activated by selecting the corresponding main menu item or by pressing the middle mouse button. The menu provides useful functions for changing display options such as zoom scale, color settings, trace display clipping, power connections display mode, etc. The main menu function is used to run a series of router passes previously defined with the main menu function. The main menu function is used to start a complete routing process including all default router passes (optional Pin-Via pre-placement, complete initial routing pass, rip-up routing on demand, and optimizer). The main menu function is used to start a single optimizer routing pass for eliminating vias, straightening trace paths and re-routing traces for better placement. The main menu function is used to load previously or partially routed chip layouts for re-entrant routing. Net list changes and current routing parameter settings are considered during trace path evaluation. The main menu function is used to return to the Chip Editor. The menu is used to set fundamental Cell Router options for subsequent router passes. These parameters define the design rules and technology requirements to be considered by the Cell Router (signal layer count, layer assignment, routing grid, standard trace width and spacing, pin contact mode, etc.). The parameters defined from the menu are stored with the layout. The menu provides system functions for exiting BAE and returning to the BAE main shell. The menu also provides functions for controlling the routing process, such as discard current routing results to prepare for router restart with new options, set the optimizer passes count, activate/deactivate multi-net pattern recognition during rip-up and/or optimization, set the persistence of the rip-up router, activate pin fanout routing and turn automatic security copy on or off. The menu provides functions for setting the strategy parameters and heuristic cost factors to be used by subsequent router and optimizer passes. 5.5.3 Cell Router System FeaturesGraphical Output and Status DisplaysThe current routing result is displayed graphically and through statistical readouts whilst routing is in progress. The number of currently routed connections (compared to the total connection count) and the global via count are continuously reported in the status line whilst during Autorouting processes. Additionally, a routing pass info window for displaying internal routing procedure information is provided on the right side of the
Cell Router user interface. This info window contains a status line for identifying the currently active router pass type
( The menu is used to set parameters for controlling graphical output. The zoom functions (, , ) are used to select the workspace to be displayed. Usually, one would use to display the complete Cell Router work area (i.e. the workspace designated by the board outline). is the default setting after starting the Cell Router. The functions for changing the zoom factor ( and ) and the function can only be executed if chip layout data is already loaded. The function of the Cell Router can also be used to load (and display) the chip layout, i.e., starts the procedures for loading the layout data if nothing was previously loaded. Note, however, that a series of Cellrouter options (see below) can not be changed anymore once the chip layout has been loaded. The
function is used to change the current color setup. The
function is used to load a predefined color table. On default the
Cell Router uses the color table named
The function is used to set the width at which circuit traces are displayed with their true widths. All traces having a screen width greater than the clipping width are displayed with their true widths. All traces having a screen width less than the clipping width are displayed as center lines. The default clipping width value is 1.5mm. The function is used to display connections to active areas using either cross-shaped markers on connected pins (option ) or airlines connecting pins and connection area gravity points (option ). On default the option is used. 5.5.4 Cell Router OptionsThe menu is used to define the design rules and technology requirements to be considered by the Cell Router. Unless ptherwise mention, Option parameters can only be set before starting the actual autorouting process. The option parameter settings are saved with the chip layout. I.e., Cell Router options need not be redefined on subsequent Cell Router calls, unless parameter changes are really required for the chip layout to be automatically routed. Routing Grid, Standard Trace Width, Standard Minimum DistanceThe Cell Router works as a grid-based router. The function from the menu is used to define the routing grid before starting the routing process. The default routing grid setting at the first Cell Router call for a particular chip layout is . The can be used to set a different routing grid. Each routing grid change is stored with the chip layout and also sets the standard trace width and minimum clearance distance values. Both the standard trace width and the standard minimum distance can be changed after specifying a new routing grid (use functions and , respectively). Note however that the sum of trace width + minimum distance must not exceed the current routing grid; otherwise the Cell Router issues an error message when starting the routing process (note warnings such as and/or , and modify trace width and/or minimum distance until either of the messages or is issued). The trace widths and minimum distance settings are usually retrieved from the process parameters provided by your chip manufacturer. The built-in off-grid recognition of the Cell Router allows for off-grid placement of pins and pre-routed traces. I.e., the Cell Router is able to connect objects which are not placed on the routing grid. Note however that on-grid items make the job much easier for the Cell Router since off-grid routing is quite time-consuming and could even prevent the Cell Router from connecting certain items in a simple way. It is recommended to use a reasonable grid for part placement to avoid off-grid pin placement and to enable pin channel routing for better routing results. Please note that smaller routing grids result in quadratic growth of memory requirements for the routing matrix, and that CPU time usage during the autorouting process rises even more dramatically (due to a non-polynomial growth of the number of possible routing solutions). It is recommended to refrain from selecting unnecessary small routing grids. The standard trace width is the track width to be used for routing the connections. The standard trace width applies for all nets except for those where certain net attributes are defined. If a
Signal Layer Count and Layer AssignmentThe function from the menu is used to specify the number of signal layers to be simultaneously routed by the Cell Router. The routing layer count can range from 2 to 12. The function is used to set the preferred routing direction (horizontal, vertical or all directions) for each routing layer. With the function it is also possible to define trace keepout layers (i.e., layers where routing is prohibited) or to remove layers from the routing layer list (which will decrement the signal layer count). The default layer assignments are horizontal for the first routing layer, vertical for the second layer, horizontal for the third layer 3, etc. Changing the routing layer count with the function resets the layer assignments. The Cellrouter simultaneously routes all routing layers. Single-layer routing can be carried out with routing layer count 2 and one of the two routing layers defined as prohibited layer. The layer assignments (except for the signal layer count) can be changed between different router passes, i.e., without the need to restart the complete routing process. Restrictions introduced with layer assignment changes will not cause a deterioration of the current routing result in subsequent router passes. I.e., the Cellrouter will try to but not necessarily remove all previously routed traces from prohibited layers, if those layers were available for routing before. Maximum Via CountThe function is used to set the maximum number of vias per circuit trace. The default maximum via count is 30. A maximum via count of 0 forces the Cell Router to rout the layout without vias. The maximum via count can be changed between different router passes, i.e., without the need of restarting the complete routing process. Lowering the maximum via count changes will not cause a deterioration of the current routing result in subsequent router passes. I.e., the Cell Router will try to but not necessarily remove previously placed vias. Via OffsetThe option controls whether the Cellrouter is allowed to place vias with an offset or not. No via offset means that vias are placed in-line with the traces (i.e., on the routing grid). Routing with via offset means that vias can be shifted by half the routing grid at their placement. The choice to offset or not must be calculated by the user taking into consideration the routing grid, trace width, clearance distance and via size. Routing with via offset may well allow to use routing channels which would otherwise be occupied by in-line placed vias on adjacent grid channels. This can have significant effect on routing success. It is recommended to refrain from routing with via offset when using larger vias since this could cause poor routing results. Sub-Grid RoutingThe function is used to activate half-grid routing (option ). On default half-grid routing is deactivated (option ). Half-grid routing means that the Cell Router can alternatively use a routing grid shifted by half of the selected routing grid, e.g., half-grid routing with 4um routing grid can also utilize the 2um routing grid. The current standard trace width and minimum distance settings are not affected by the sub-grid routing option. Half-grid routing yields better use of regions nearby off-grid placed objects such as pin channels at off-grid placed parts, thus considerably increasing routability of dense layouts. Pin Contact ModeThe function is used to allow (option ) or avoid (option , default) pin corner routing. This feature works on approximately rectangle-shaped pads and controls whether traces can exit such pads at 45 degree angles or not. Routing with pin corner obstruction can produce better looking layouts, but could also impede 100% routing. Note that connecting pins with a size approximately equal to or smaller than the trace width could fail. The option should not be used with designs that include thick traces. Note also that bus routing can produce unpredictable results when switched to pin corner obstruction. 5.5.5 Cell Router ControlThe menu provides a series of functions for controlling the routing process. Router RestartThe function discards the previous routing result. This function can be used to restart the routing process with new routing options and strategies. Optimizer PassesThe function is used to set the number of Optimizer routing passes to be automatically activated by the function after obtaining a 100% routing. The Optimizer passes count can range from 0 to 99; 2 Optimizer passes are activated on default. Router Cleanup, Optimizer CleanupThe function is used to activate (default option ) or deactivate (option ) cleanup passes during rip-up routing. The function is used to activate (default option ) or deactivate (option ) cleanup passes during optimization. When running cleanup passes (note message issued by the routing progress report), the Cellrouter makes use of a unique pattern search recognition algorithm for identifying disturbing traces during rip-up and cross-net optimization. The Cellrouter is able to select and remove disturbing traces during rip-up and perform cross-net changes during optimization. Cleanup during cross-net optimization usually reduces via counts dramatically and thus is also called if the rip-up router (temporarily) fails to find an acceptable solution. It is recommended to refrain from turning off cleanup when running rip-up on complex designs or optimizing dense chip layouts. Turning cleanup off results in sequential processing of the connections and can produce contenting results when running final Optimizer passes on certain layouts (however, more passes are then required for pushing and/or straightening trace bunches). Rip-Up Trees, Rip-Up Depth, Rip-Up RetriesThe function sets the maximum number of traces allowed to be simultaneously ripped up per rip-up cycle. The rip-up trees number is set to 2 on default, and can range from 1 to 9. The function is used to control the persistence of the rip-up process. A high value will result in higher persistence. The rip-up depth value can range from 1 to 999, and is set to 50 on default. The function sets the maximum number of rip-up retries for routing a particular trace, thus defining the local rip-up router intensity. The rip-up retries number is set to 2 on default, and can range from 0 to 99. Higher rip-up control parameters increase the persistence and intensity of the rip-up routing process, and thus can be used for special problems such as completing 100% routing without intermediate optimizer passes or for routability check. Once 99.5% routing completion is achieved, the Rip-Up parameters are automatically increased to Rip-Up Trees 6, Rip-Up Level 200 and Rip-Up Retries 10, unless higher values are already set. This helps to avoid the time-consuming Optimizer cleanup passes between Rip-Up passes if only a few open connections are left. Pin Via Pre-PlaceThe function is used to activate (option ) or deactivate (default option ) the initial routing algorithm for connecting cell pins to signal inside layers. With pin fanout routing activated the function will start with the pin via pre-place initial routing pass. The fanout router creates short trace stubs to connect netlist pins to vias. The fanout router ignores any layer-specific routing direction preferences to avoid pin channel obstructions. The purpose of the fanout router is to prevent the Cell Router from blocking pin rows through extensive use of the cell/pin layers at an early stage of the routing process. The pin via router does not (re-)rout pins which are already connected to fixed traces. Redundant pin via connections are later eliminated by the Optimizer. Security CopyThe function is used to activate (default) or deactivate automatic security copy of intermediate routing results. 5.5.6 Cell Router StrategyThe menu provides functions for setting routing strategies such as via cost, pin channel cost, packing cost, bus bending cost, dynamic density cost, etc. These settings should be used with care. Only change one or two at a time. Poor routing results are often found to be caused by random strategy parameter settings. The default settings will work best in the vast majority of cases. It is strongly recommended to change strategy parameters in special cases only and to refrain from using extreme values. There are strong mutual dependencies between different Cell Router strategy parameters. A high via cost value (for eliminating vias) will necessarily result in more ignorance of routing direction preferences, thus compensating the cost factor for keeping preferred routing directions. Note also that strategy parameters only define subordinate options for the routing process, due to the fact that it is much more important to achieve a 100% routing result instead of, e.g., keeping preferred routing directions. I.e., some cost factors may be completely ignored during initial routing and rip-up and will only be considered by the Optimizer. Tabelle 5-1 provides an overview to all of the routing parameters which can be set from the Strategy menu. Table 5-1: Cell Router Strategy Parameters
Optimize DirectionThe function is used to designate the Optimizer strategy. The default option causes the Optimizer to ignore layer-specific preferred routing directions in order to obtain the greatest reduction of vias. The option causes the Optimizer to consider layer-specific preferred routing directions, which could increase the number of vias. The option causes the Optimizer to prefer diagonal (45 degree) routing where appropriate. Via CostThe setting is used by the Router and the Optimizer. A high via cost factor results in fewer vias but more complex circuit traces. A low via cost factor permits more vias within the restraint of the maximum via count (see above). The via cost value can range from 2 to 20; the default value is 10. Pin Channel CostThe setting is used by the Router only. A high pin channel cost factor results in infrequent use of pin channels. A low pin channel cost factor permits the frequent use of pin channels. Pin channels are the regions between adjacent part pins. The pin channel cost value can range from 2 to 20; the default value is 10. Counter Direction CostThe setting is used by the Router and the Optimizer. A high counter direction cost factor results in strict adherence to the layer-specific preferred routing directions. A low cost factor permits frequent variations from the preferred direction. The counter direction cost value can range from 0 to 5; the default value is 1. Direction Change CostThe setting is used by the Optimizer only. A high direction change cost factor results in less circuit corners. A low direction change cost factor permits frequent changes in routing directions. The direction change cost value can range from 0 to 5; the default value is 2. Packing CostThe setting is used by the Router only. A high packing cost factor results in high bundling of circuit traces. A low packing cost factor will result in wider distribution of circuit traces. The packing cost value can range from 0 to 5; the default value is 1. Dynamic Density CostThe setting is used by the Router only. The dynamic density cost factor controls the global distribution of circuit traces over the entire layout. A high dynamic density cost factor results in a more even distribution of the circuit traces. A low cost factor gives more influence to routing costs. The dynamic density cost value can range from 0 to 50; the default value is 10. Bus Bending CostThe setting is used by the Router only. The bus bending cost factor controls the bending of traces after passing a pin channel. A high bus bending cost factor results in high priority of bending. A low bus bending cost factor results in less bending. The bus bending cost value can range from 0 to 5; the default value is 2. Rip-Up Distance CostThe and settings are used by the Router during rip-up. The rip-up distance-1 cost factor controls the use of channels left by ripped up traces in the near distance (0 to 1 grid point). A high distance-1 cost factor results in less use of these channels, thus forcing more local changes during rip-up and retry routing. The rip-up distance-1 cost value can range from 0 to 10; the default value is 5. The rip-up distance-2 cost factor controls the use of channels left by ripped up traces in the far distance (2 grid points). A high distance-2 cost factor results in less use of these channels, thus forcing more global changes during rip-up and retry routing. The rip-up distance-2 cost value can range from 0 to 10; the default value is 2. Trace Crossing CostThe is used to set the trace transition cost factor, which is considered by the Router and the Optimizer to control cleanup pattern recognition during multi-net optimization. A high trace crossing cost factor allows for a more complex routing with more traces crossing each other, thus also producing more vias. A low trace crossing cost factor leads to increased (and more time-consuming) analysis during cross-net optimization, thus eliminating more vias. The trace crossing cost value can range from 2 to 100; the default value is 10. Diagonal Routing CostThe Optimizer considers the setting on routing layers where the routing option is selected (see function above). A high diagonal routing cost factor causes the Optimizer to use more diagonal routes. A low diagonal routing cost factor results in less diagonal routing. The diagonal cost value can range from 0 to 10; the default value is 5. Off-Grid Routing CostThe setting is used by the Router and the Optimizer, and is considered when routing with the half-grid option (see above). A high off-grid routing cost factor results in less use of the sub-grid. A low off-grid routing cost factor permits frequent use of the sub-grid. The off-grid routing cost value can range from 0 to 5; the default value is 2. 5.5.7 Cell Router FunctionsSome of the actual autorouting procedures provided with the Cell Router can be called from the main menu, others can be activated using either router control parameters or the and functions (see below). The current routing result is displayed graphically and through statistical readouts whilst routing is in progress. The routing process can be stopped at any time by pressing a key, causing the Cell Router to revert to the (currently best) routing result. Pin Via Pre-Placeis a special initial routing algorithm for connecting netlist pins to other layers through short trace stubs with single vias. A channel width setting is required for these fanout routing passes. The fanout router doesn't consider layer-specific preferred routing direction settings. The purpose of pin via pre-routing is to prevent the Cell Router from extensively using the cell/pin layers at an early stage of the routing process. This strategy achieves earlier 100% routing success in a range of designs. Redundant via connections created by are later eliminated by the . Single-Pass Initial RoutingThe single-pass Initial Router performs signal trace routing considering preferred routing directions, a certain channel width and a maximum via count per two-point connection. The channel width is the maximum permitted deviance from preferred directions. The channel width is specified in routing grid steps. A zero channel width removes the restraints on deviating from the preferred direction, i.e., the entire board area is then released for routing. The maximum via count used by the Initial Router will never exceed the value set with the function from the menu (see above). The Initial Router places traces close together, thus using minimum space in order to leave more room for subsequent traces (trace hugging). The Initial Router also uses advanced techniques of copper sharing where appropriate. The Initial Router processes power layer connections and attributed nets (with non-default routing widths, minimum distance settings and routing priorities) with highest priority. Complete Initial RoutingThe Complete Initial Router automatically activates four Initial Router passes to rout all open connections which can be routed without rip-up and retry. With each Initial Router pass the channel width and the maximum via count is increased. The first Initial Router pass runs with maximum via count zero. The last Initial Router pass runs with channel width zero and a maximum via count according to the parameter set with the function from the menu (see above). Rip-Up/Retry RouterThe Rip-Up/Retry Router attempts to route all open connections until the board is completely routed. Connections which can be routed without rip-up are routed first. Then the Rip-Up/Retry Router selects and eliminates traces (rip-up) and re-routes them to create space for the unroutes. For this purpose, the router gathers information on dense board areas and increases the cost of routing in such areas. The Rip-Up/Retry Router is supported by a sophisticated array of heuristic strategy parameters. The cost factors can be dynamically adapted to the current routing problem, thus controlling the "price" of strategies such as via placement, routing against preferred directions, using pin channels, etc. It is strongly recommended to refrain from modifying these strategies, unless the routing success is not what would be expected. When changing cost factors, slight adjustments to a few can make significant improvements or make things much worse. The Rip-Up/Retry Router is guarded by a unique backtracking algorithm, which not only prevents from a deterioration of the result or a dead-lock during rip-up or optimization but also is able to exploit a new and/or better routing solution. The Rip-Up/Retry Router automatically activates intermediate Optimizer passes if a single rip-up pass fails to achieve 100% routing success. OptimizerThe function is used to start a single pass. The usually is applied after 100% routing to optimize the layout for manufacturing. The eliminates redundant vias, smoothes traces and attempts to rout open connections. Channel width zero is used during optimization and the maximum via count is set to the same value as defined with the function from the menu (see above). Full CellrouterThe main menu function is used to start a complete routing process including all router passes such as Pin Via Pre-Placement (optionally), complete initial routing, rip-up/retry routing (if necessary) and optimization. This is the standard procedure for performing complete routing of the chip layout. The number of final passes can be set with the function from the menu (see above). The Pin Via Pre-Placer is only activated if the option has been selected with the function from the menu. Load LayoutThe function is used to load previously or partially routed layouts to prepare for re-entrant routing. Before starting the function, the Cell Router options and strategies should be set as required (see above). Fixed traces (and vias) are left unchanged. Unfixed traces are evaluated considering changed part placement, current via assignments, modified keepout and power plane definitions, net list changes, and current Cell Router parameter settings (routing grid, standard trace width, corner cutting, clearance, etc.). The function tries to adjust unfixed traces to conform with the design rules. Arc-shaped trace segments are replaced by straight segments where possible. Unfixed traces not adjustable to the design rules are completely or partially discarded. The function can be used to complete the routing after (re-entrant routing). Batch Setup and Batch StartThe function is used to start a routing process with different user-defined router passes. The function is used to schedule up to ten of the following autorouting procedures to be subsequently processed with the function:
pass requires a routing channel width specification and a maximum via count setting. requires a routing channel width specification. requires the number of required passes (up to 999). 5.6 IC Design Data Import and Export5.6.1 GDS Data Import and OutputSorry, this information is currently being updated. 5.6.2 CIF Data Import and OutputSorry, this information is currently being updated.
IC/ASIC Design |
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